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What is differnce between verilog & VHDL
please introduce me a verilog compiler for android
2 Answers
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verilog and vhdl both are hardware description languages.
verilog looks like near to c ans c++
but vhdl is like some new kind. Both do samd job to design and testing the modules in an chip design
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VHDL is more verbose than Verilog and it is also has a non-C like syntax. With VHDL, you have a higher chance of writing more lines of code. Verilog has a better grasp on hardware modeling, but has a lower level of programming constructs. Verilog is not as verbose as VHDL so that's why it's more compact.
https://blog.digilentinc.com/battle-over-the-fpga-vhdl-vs-verilog-who-is-the-true-champ/