+ 3

What is differnce between verilog & VHDL

please introduce me a verilog compiler for android

25th Apr 2018, 9:23 AM
Mohammadian Mohammad
Mohammadian Mohammad - avatar
2 Answers
+ 4
verilog and vhdl both are hardware description languages. verilog looks like near to c ans c++ but vhdl is like some new kind. Both do samd job to design and testing the modules in an chip design
23rd May 2018, 1:46 AM
Vijay Kumar Kanchukommala
Vijay Kumar Kanchukommala - avatar
+ 2
VHDL is more verbose than Verilog and it is also has a non-C like syntax. With VHDL, you have a higher chance of writing more lines of code. Verilog has a better grasp on hardware modeling, but has a lower level of programming constructs. Verilog is not as verbose as VHDL so that's why it's more compact. https://blog.digilentinc.com/battle-over-the-fpga-vhdl-vs-verilog-who-is-the-true-champ/
26th Apr 2018, 1:31 PM
Tyler Abbott
Tyler Abbott - avatar