Which of the following statements is false?

Question

A) Verilog does not allow module ports that are not connected.

 B) Verilog allows module ports to be not connected.

C) Verilog allows module ports to be connected.

Answer 1

I don’t think you really understand what the Q&A section is for.

It’s not for making small quizzes for people to do, if you want that then you should look at the quiz factory. It’s for when you have a question or something to say. This is probably why you haven’t gotten many answers.